VLSI tools (EDA)

経験内容

15 years at *Cadence*, in *(EDA) Electronic Design Automation* tools space working in system level design, logic design and verification, assertion based verification, verification management etc. Skilled in C/C++, System Verilog, SystemC, Specman e, Software Development, Management of software development process, defining product roadmap and delivery management etc.

氏名・職歴の開示について

氏名:(開示前)

職歴:(開示前)


自己紹介

Having worked in different technology domains of embedded systems (for different products/applications), system-level design (ESL), Logic design verification (which includes transaction, assertion, acceleration, formal and verification-planning approaches), I endeavor to excel in the domain of challenging/complex technologies and their applications, while taking into account the business/commercial aspects. My objective is to attain the highest levels of quality in technology delivery. I enjoy leading, motivating and directing team of ambitious, self-starters, highly capable engineers.

Skills:
- Embedded systems
- System-level design (ESL)
- Assertion-based verification (ABV)
- Transaction-based verification
- Hardware-assisted acceleration
- Formal verification/Model checking
- Verification-planning and management
- Verification IP development
- Customer engagements
- Cross-geographic/cross-functional management
- Business prioritization and resource planning
- People management
- Product management

職歴

開示前(決済前には開示されます)